Computer arrangements, including microprocessors and digital signal processors, have been designed for a wide range of applications and have been used in virtually every industry. For a variety of reasons, many of these applications have been directed to processing video data and have demanded minimal levels of power consumption and compactness. Some applications have further demanded a high-speed computing engine that can perform effectively on a real-time or near real-time basis. Many of these video-processing applications have required a data-signal processing circuit that is capable of performing multiple functions at ever-increasing speeds.
Increasing the power and versatility of such computing engines, however, can undermine other important goals. For example, faster computing engines consume more power and circuit real estate, whereas the ideal engine minimizes both power consumption and the amount of circuitry required to implement the computing engine.
Moreover, providing versatility and high power typically exacerbates the circuit real estate problem by requiring various types of processing circuitry, each specialized and selectively activated for different processing functions. This phenomena can be appreciated when comparing, for instance, relatively-slow general-purpose processing in video applications versus specialized video-signal filter processing used for compressing and decompressing video data in real time. Because the specialized processing circuitry is typically optimized to keep up with the real-time speeds of the video data, it is often difficult to provide a single video-data processing circuit that is adequately versatile without providing seemingly excess circuitry useful only for limited applications.
As a more particular example, many video-signal processing applications employ specialized video-signal filters for vertical signal processing which uses a specialized video-data filter known as a “polyphase” filter. In video-processing applications, a polyphase filter is used to resize pixels by manipulating data stored to represent the horizontal and vertical lines used to refresh the display. In such applications, expansion or up-sampling (“zoom-factor” greater than one) is achieved by increasing the ratio of the number of output pixels to the number of input pixels; whereas, compression or down-sampling (“zoom-factor” less than one) is achieved by decreasing the ratio of the number of output pixels to the number of input pixels.
Another particular type of video-signal processing application includes motion compensation and may employ devices such as multimedia coprocessors designed for motion compensated scan rate conversion. Motion compensation may be achieved by deinterlacing incoming fields followed by subsequent up conversion, both being based on motion information estimated and embedded in the form of motion vectors.
Conventional motion estimation includes scanning a row of 16 horizontally adjacent 8×8 pixel blocks by scanning all of the lines in an entire pixel block before moving on to scan adjacent pixel blocks. In order to accommodate a motion vector range, a horizontal width including additional pixels is needed. For example, to accommodate +/−60 pixels in the horizontal direction, a width of (16×8)+(2×60)=248 pixels is needed. In addition, 4 additional pixels are needed at each end for processing border blocks, resulting in 256 pixels in the horizontal direction. Similarly, in the vertical direction, 8+ (2×16)+8=48 lines are needed, along with 8 additional lines for updating data for the next 16 8×8 adjacent rows, resulting in 56 lines in the vertical direction.
This conventional motion estimation, relying upon scanning an entire pixel block before moving on to scan adjacent pixel blocks, and resulting in 56 lines scanned in the vertical direction in the specific example discussed above, presents many challenges. For example, buffers used in the motion correction must have sufficient lines to be able to accommodate the scanned lines. This results in a relatively large buffer, high power consumption and high latency for the scan.
The present invention is directed to goals including the above-mentioned and the minimization of line buffer usage, power consumption and latency in motion compensation and other types of pixel-data processing.